module pwm
(
    input   wire        sys_clk,// 120uS
    input   wire        sys_rst_n,
    input   wire [1:0]  mode,
    output  wire        out
);
parameter _100_MS = 834;
parameter _10_100_MS = 10;

reg     [9:0]   cnt;
reg     [3:0]   cnt_ms;// 

always@(posedge sys_clk or  negedge sys_rst_n)
    if(!sys_rst_n)
        cnt    <=  'd0;
    else if(cnt == (_100_MS -1'b1))
        cnt    <=  'd0;
    else 
        cnt    <=  cnt + 'b1;
 
always@(posedge sys_clk or  negedge sys_rst_n)
    if(!sys_rst_n)
        cnt_ms <=  'h0;
    else if((cnt == (_100_MS -1'b1)) & (cnt_ms == (_10_100_MS -1'b1)) )
        cnt_ms <=  'h0;
    else if(cnt == (_100_MS -1'b1))
        cnt_ms <=  cnt_ms +'h1;

assign out =    (mode==2'b01) ? 1'b0 :
                (mode==2'b10) ? (cnt_ms[0:0]=='b1) :
                (mode==2'b11) ? (cnt_ms =='h00) :
                1'b1;
endmodule
